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| INTEGRATED CIRCUITS DATA SHEET TDA8754 Triple 8-bit video ADC up to 270 Msps Preliminary specification Supersedes data of 2003 Jul 16 2003 Sep 30 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.1.1 9.1.2 9.1.3 9.2 9.3 9.4 9.5 9.6 9.7 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING LQFP144 package LBGA208 package FUNCTIONAL DESCRIPTION Power management Standby mode Power-down mode Analog video input Analog multiplexers Activity detection ADC Clamp AGC HSOSEL, DEO and SCHCKREFO PLL Sync-on-green Programmable coast Data enable Sync separator 3-level I2C-BUS REGISTER DESCRIPTION I2C-bus formats Write 1 register Write all registers Read register I2C-bus registers overview Offset registers (R, G and B) Coarse registers (R, G and B) Fine registers (R, G and B) SOG register PLL control 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20 TDA8754 Phase register PLL divider registers Horizontal sync registers Coast register Horizontal sync selection register Vertical sync selection register Clamp register Inverter register Output register Output enable register 1 Output enable register 2 Clock output register Internal oscillator register Power management register Read register Version register Sign detection register Activity detection register 1 Activity detection register 2 LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2003 Sep 30 2 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 1 FEATURES TDA8754 * 3.3 V power supply * Triple 8-bit ADC * Analog sampling rate from 12 up to 270 Msps * Maximum data rate: - Single port mode: 140 MHz - Dual port mode: 270 MHz - 3.3 V LV-TTL outputs. * PLL control via I2C-bus: - Low PLL drift with temperature (2 phase steps maximum) - PLL generates the ADC sampling clock which can be locked on the line frequency from 15 to 150 kHz - Integrated PLL divider - Programmable phase clock adjustment cells. * Three clamp circuits for programming a clamp code from -24 to +136 by steps of 1 LSB (mid-scale clamping for YUV signal) * Internal generation of clamp signal * Three independent blanking functions * Input: - 410 MHz analog bandwidth - Two independent analog inputs selectable via I2C-bus - Analog input from 0.5 to 1 V (p-p) to produce a full-scale ADC input of 1 V (p-p) - Three controllable amplifiers: gain control via I2C-bus to produce full-scale peak-to-peak output with a half LSB resolution. * Synchronisation: - Frame and field detection for interlaced video signal - Parasite synchronization pulse detection and suppression - Sync processing for composite sync, 3-level sync and sync-on-green signals - Polarity and activity detection. * IC control via I2C-bus serial interface * Power-down mode. 2 APPLICATIONS * RGB/YUV high-speed digitizing * LCD panels drive * LCD projection system * New TV concept. 3 GENERAL DESCRIPTION The TDA8754 is a complete triple 8-bit ADC with an integrated PLL running up to 270 Msps and analog preprocessing functions (clamp and PGA) optimized for capturing RGB/YUV graphic signals. The PLL generates a pixel clock from inputs HSYNC and COAST. The TDA8754 offers full sync processing for sync-on-green applications. A clamp signal may be generated internally or provided externally. The clamp levels, gains and other settings are controlled via the I2C-bus interface. This IC supports display resolutions up to QXGA (2048 x 1536) at 85 Hz. 2003 Sep 30 3 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 4 QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO fPLL ENOB INL DNL Ptot 5 PARAMETER analog supply voltage digital supply voltage output supply voltage analog PLL frequency effective number of bits integral non-linearity differential non-linearity power dissipation fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz CONDITIONS MIN. 3.0 3.0 3.0 12 - - - - TYP. 3.3 3.3 3.3 - 7.6 0.6 0.25 1 TDA8754 MAX. 3.6 3.6 3.6 270 - 1.3 0.6 1.3 UNIT V V V MHz bits LSB LSB W ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP144 DESCRIPTION plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm VERSION SOT486-1 SAMPLING FREQUENCY 110 MHz 140 MHz 170 MHz 210 MHz 250 MHz 270 MHz LBGA208(1) plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm SOT774-1 110 MHz 140 MHz 170 MHz 210 MHz 250 MHz 270 MHz TDA8754HL/11 TDA8754HL/14 TDA8754HL/17 TDA8754HL/21 TDA8754HL/25 TDA8754HL/27 TDA8754EL/11 TDA8754EL/14 TDA8754EL/17 TDA8754EL/21 TDA8754EL/25 TDA8754EL/27 Note 1. Values are not yet guarantee. 2003 Sep 30 4 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 6 BLOCK DIAGRAM TDA8754 handbook, full pagewidth 3x 3x CLAMP AGC 3x ADC DMX LV-TTL BUFFERS RGB output B ACTIVITY DETECTION HPDO LV-TTL BUFFERS RGB output A RGB1 input RGB2 input TDA8754 SOGIN1 SOGIN2 HSYNC1 CHSYNC1 HSYNC2 CHSYNC2 COAST PLL VSYNC1 VSYNC2 I 2 C-BUS SLAVE POWER MANAGEMENT SYNC SEPARATOR CLKDMX HCOUNTER CKDATA DEO MGU895 VSYNCO HSYNCO CKEXT CKREFO SDA SCL A0 FIELDO Fig.1 Block diagram. 2003 Sep 30 5 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 7 7.1 PINNING LQFP144 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TTL input digital ground TTL input digital supply voltage horizontal synchronization pulse input 2 composite horizontal synchronization pulse input 2 PLL analog supply voltage horizontal synchronization pulse input 1 composite horizontal synchronization pulse input 1 PLL analog ground PLL filter input CPO analog ground PLL filter input phase measurement output (test) SUB analog ground decoupling SOG input 1 decoupling SOG output decoupling SOG input 2 SOG analog ground sync-on-green input 1 SOG analog supply voltage sync-on-green input 2 red channel analog supply voltage red channel analog input 1 red channel 1 analog ground red channel analog input 2 red channel 2 analog ground main regulator decoupling input red channel ladder decoupling input red channel clamp capacitor input green channel analog supply voltage green channel analog input 1 green channel 1 analog ground green channel analog input 2 green channel 2 analog ground green channel ladder decoupling input green channel clamp capacitor input blue channel analog supply voltage blue channel analog input 1 blue channel 1 analog ground DESCRIPTION TDA8754 SYMBOL GNDD(TTL) VCCD(TTL) HSYNC2 CHSYNC2 VCCA(PLL) HSYNC1 CHSYNC1 GNDA(PLL) CZ GNDA(CPO) CP PMO GNDA(SUB) CAPSOGIN1 CAPSOGO CAPSOGIN2 GNDA(SOG) SOGIN1 VCCA(SOG) SOGIN2 VCCA(R) RIN1 GNDA(R1) RIN2 GNDA(R2) DEC RBOT RCLPC VCCA(G) GIN1 GNDA(G1) GIN2 GNDA(G2) GBOT GCLPC VCCA(B) BIN1 GNDA(B1) 2003 Sep 30 6 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL BIN2 GNDA(B2) BBOT BCLPC AGCO GNDD(ADC) VCCD(ADC) GNDD(SUB) PWD TEST BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 VCCO(BB) GNDO(BB) BOR BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 VCCO(BA) GNDO(BA) GB0 GB1 GB2 GB3 GB4 GB5 GB6 GB7 VCCO(GB) GNDO(GB) 2003 Sep 30 PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 blue channel analog input 2 blue channel 2 analog ground DESCRIPTION blue channel ladder decoupling input blue channel clamp capacitor input AGC output ADC digital ground ADC digital supply voltage SUB digital ground power-down control input test input; must be connected to ground blue channel ADC output B bit 0 blue channel ADC output B bit 1 blue channel ADC output B bit 2 blue channel ADC output B bit 3 blue channel ADC output B bit 4 blue channel ADC output B bit 5 blue channel ADC output B bit 6 blue channel ADC output B bit 7 blue channel B output supply voltage blue channel B output ground blue channel ADC output bit out of range blue channel ADC output A bit 0 blue channel ADC output A bit 1 blue channel ADC output A bit 2 blue channel ADC output A bit 3 blue channel ADC output A bit 4 blue channel ADC output A bit 5 blue channel ADC output A bit 6 blue channel ADC output A bit 7 blue channel A output supply voltage blue channel A output ground green channel ADC output B bit 0 green channel ADC output B bit 1 green channel ADC output B bit 2 green channel ADC output B bit 3 green channel ADC output B bit 4 green channel ADC output B bit 5 green channel ADC output B bit 6 green channel ADC output B bit 7 green channel B output supply voltage green channel B output ground 7 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL GOR GA0 GA1 GA2 GA3 GA4 GA5 GA6 GA7 VCCO(GA) GNDO(GA) RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 VCCO(RB) GNDO(RB) ROR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VCCO(RA) GNDO(RA) VCCO(CLK) CKDATA GNDO(CLK) GNDD(I2C) VCCD(I2C) A0 SDA SCL DIS 2003 Sep 30 PIN 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 green channel ADC output A bit 0 green channel ADC output A bit 1 green channel ADC output A bit 2 green channel ADC output A bit 3 green channel ADC output A bit 4 green channel ADC output A bit 5 green channel ADC output A bit 6 green channel ADC output A bit 7 DESCRIPTION green channel ADC output bit out of range green channel A output supply voltage green channel A output ground red channel ADC output B bit 0 red channel ADC output B bit 1 red channel ADC output B bit 2 red channel ADC output B bit 3 red channel ADC output B bit 4 red channel ADC output B bit 5 red channel ADC output B bit 6 red channel ADC output B bit 7 red channel B output supply voltage red channel B output ground red channel ADC output bit out of range red channel ADC output A bit 0 red channel ADC output A bit 1 red channel ADC output A bit 2 red channel ADC output A bit 3 red channel ADC output A bit 4 red channel ADC output A bit 5 red channel ADC output A bit 6 red channel ADC output A bit 7 red channel A output supply voltage red channel A output ground clock output digital supply voltage data clock output clock output digital ground I2C-bus lines digital ground I2C-bus lines digital supply voltage I2C-bus address control input I2C-bus serial data input and output I2C-bus serial clock input I2C-bus disable control input 8 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL TDO TCK CLP STBYDIV GNDD(MCF) VCCD(MCF) HSYNCO DEO HPDO GNDO(TTL) VCCO(TTL) VSYNCO FIELDO CLPO CKREFO CSYNCO ACRX2 ACRX1 GNDD(SLC) VCCD(SLC) CKEXT COAST VSYNC2 VSYNC1 PIN 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 scan test output DESCRIPTION scan test mode input; must be connected to ground clamp pulse input DVI standby output MCF digital ground MCF digital supply voltage horizontal synchronization pulse output data enable output hot plug detector output TTL output digital ground TTL output digital supply voltage vertical synchronization pulse output field information output clamp output reference output clock; re-synchronized horizontal negative pulse composite synchronization output test pin; should be connected to ground test pin; should be connected to ground SLC digital ground SLC output digital supply voltage external clock input PLL coast control input vertical synchronization pulse input 2 vertical synchronization pulse input 1 handbook, halfpage 108 73 109 72 TDA8754HL 144 37 1 36 MGU896 Fig.2 Pin configuration LQFP144 package. 2003 Sep 30 9 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 7.2 LBGA208 package BALL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 sync-on-green input 1 PLL analog ground sync-on-green input 2 PLL analog ground horizontal synchronization pulse input 2 composite horizontal synchronization pulse input 2 PLL coast control input composite synchronization output field information output horizontal synchronization pulse output I2C-bus serial clock input not connected not connected I2C-bus disable control input I2C-bus address control input data clock output PLL analog ground phase measurement output (test) PLL analog ground PLL analog ground PLL analog supply voltage clamp pulse input external clock input reference output clock; re-synchronized horizontal negative pulse vertical synchronization pulse output data enable output I2C-bus serial data input and output not connected not connected not connected clock output digital ground clock output digital supply voltage red channel analog input 1 analog ground decoupling SOG input 1 decoupling SOG input 2 decoupling SOG output horizontal synchronization pulse input 1 vertical synchronization pulse input 1 clamp output 10 DESCRIPTION TDA8754 SYMBOL SOGIN1 GNDA(PLL) SOGIN2 GNDA(PLL) HSYNC2 CHSYNC2 COAST CSYNCO FIELDO HSYNCO SCL n.c. n.c. DIS A0 CKDATA GNDA(PLL) PMO GNDA(PLL) GNDA(PLL) VCCA(PLL) CLP CKEXT CKREFO VSYNCO DEO SDA n.c. n.c. n.c. GNDO(CLK) VCCO(CLK) RIN1 GNDA CAPSOGIN1 CAPSOGIN2 CAPSOGO HSYNC1 VSYNC1 CLPO 2003 Sep 30 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL n.c. n.c. TCK TDO VCCD(I2C) n.c. n.c. n.c. GNDA GNDA CZ CP GNDA(CPO) CHSYNC1 VSYNC2 HPDO n.c. n.c. VCCO(TTL) GNDO(TTL) GNDD(I2C) n.c. n.c. n.c. RIN2 GNDA GNDA GNDA GNDD(TTL) VCCD(TTL) GNDD(SLC) VCCD(SLC) n.c. n.c. n.c. n.c. GNDA GNDA RBOT GNDA n.c. 2003 Sep 30 BALL C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E7 E8 E9 E10 E13 E14 E15 E16 F1 F2 F3 F4 F13 not connected not connected scan test mode input scan test output I2C-bus lines digital supply voltage not connected not connected not connected analog ground analog ground PLL filter input PLL filter input CPO analog ground DESCRIPTION composite horizontal synchronization pulse input 1 vertical synchronization pulse input 2 hot plug detector output not connected not connected TTL output digital supply voltage TTL output digital ground I2C-bus lines digital ground not connected not connected not connected red channel analog input 2 analog ground analog ground analog ground TTL input digital ground TTL input digital supply voltage SLC digital ground SLC output digital supply voltage not connected not connected not connected not connected analog ground analog ground red channel ladder decoupling input analog ground not connected 11 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL n.c. n.c. n.c. GIN1 GNDA DEC VCCA VCCA n.c. n.c. n.c. n.c. n.c. GNDA GNDA GNDA RCLPC VCCA n.c. n.c. n.c. n.c. n.c. GIN2 GNDA GBOT GNDA GCLPC n.c. n.c. n.c. n.c. n.c. GNDA GNDA GNDA BCLPC VCCA n.c. n.c. n.c. 2003 Sep 30 BALL F14 F15 F16 G1 G2 G3 G4 G5 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K12 K13 K14 not connected not connected not connected green channel analog input 1 analog ground main regulator decoupling input analog supply voltage analog supply voltage not connected not connected not connected not connected not connected analog ground analog ground analog ground red channel clamp capacitor input analog supply voltage not connected not connected not connected not connected not connected green channel analog input 2 analog ground DESCRIPTION green channel ladder decoupling input analog ground green channel clamp capacitor input not connected not connected not connected not connected not connected analog ground analog ground analog ground blue channel clamp capacitor input analog supply voltage not connected not connected not connected 12 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL n.c. n.c. BIN1 GNDA BBOT VCCA n.c. n.c. n.c. n.c. GNDA GNDA AGCO TEST VCCO VCCO GNDO GNDO n.c. n.c. n.c. n.c. BIN2 GNDA GNDD(ADC) GNDD(ADC) BA2 VCCO GB4 GB0 GA4 GA0 GNDO PWD n.c. n.c. n.c. n.c. VCCD(ADC) VCCD(ADC) BB1 2003 Sep 30 BALL K15 K16 L1 L2 L3 L4 L13 L14 L15 L16 M1 M2 M3 M4 M7 M8 M9 M10 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 not connected not connected blue channel analog input 1 analog ground DESCRIPTION blue channel ladder decoupling input analog supply voltage not connected not connected not connected not connected analog ground analog ground AGC output test input data output digital supply voltage data output digital supply voltage data output digital ground data output digital ground not connected not connected not connected not connected blue channel analog input 2 analog ground ADC digital ground ADC digital ground blue channel ADC output A bit 2 data output digital supply voltage green channel ADC output B bit 4 green channel ADC output B bit 0 green channel ADC output A bit 4 green channel ADC output A bit 0 data output digital ground power-down control input not connected not connected not connected not connected ADC digital supply voltage ADC digital supply voltage blue channel ADC output B bit 1 13 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL BA6 BA3 BOR GB5 GB1 GA5 GA1 RB6 RB3 RB0 RA5 RA2 ROR BB6 BB4 BB2 BA7 BA4 BA0 GB6 GB2 GA6 GA2 RB7 RB4 RB1 RA6 RA3 RA0 BB7 BB5 BB3 BB0 BA5 BA1 GB7 GB3 GA7 GA3 GOR RB5 2003 Sep 30 BALL P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 blue channel ADC output A bit 6 blue channel ADC output A bit 3 DESCRIPTION blue channel ADC output bit out of range green channel ADC output B bit 5 green channel ADC output B bit 1 green channel ADC output A bit 5 green channel ADC output A bit 1 red channel ADC output B bit 6 red channel ADC output B bit 3 red channel ADC output B bit 0 red channel ADC output A bit 5 red channel ADC output A bit 2 red channel ADC output bit out of range blue channel ADC output B bit 6 blue channel ADC output B bit 4 blue channel ADC output B bit 2 blue channel ADC output A bit 7 blue channel ADC output A bit 4 blue channel ADC output A bit 0 green channel ADC output B bit 6 green channel ADC output B bit 2 green channel ADC output A bit 6 green channel ADC output A bit 2 red channel ADC output B bit 7 red channel ADC output B bit 4 red channel ADC output B bit 1 red channel ADC output A bit 6 red channel ADC output A bit 3 red channel ADC output A bit 0 blue channel ADC output B bit 7 blue channel ADC output B bit 5 blue channel ADC output B bit 3 blue channel ADC output B bit 0 blue channel ADC output A bit 5 blue channel ADC output A bit 1 green channel ADC output B bit 7 green channel ADC output B bit 3 green channel ADC output A bit 7 green channel ADC output A bit 3 green channel ADC output bit out of range red channel ADC output B bit 5 14 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL RB2 RA7 RA4 RA1 BALL T13 T14 T15 T16 red channel ADC output B bit 2 red channel ADC output A bit 7 red channel ADC output A bit 4 red channel ADC output A bit 1 DESCRIPTION handbook, halfpage MBL890 T R P N M L K J H G F E D C B A 1 2 3 4 5 TDA8754EL 6 7 8 9 10 11 12 13 14 15 16 Fig.3 Pin configuration LBGA208 package. 2003 Sep 30 15 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 8 FUNCTIONAL DESCRIPTION 8.2.1 ANALOG MULTIPLEXERS TDA8754 This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals coming from an analog source into digital data used by a LCD driver (pixel clock up to 270 MHz with analog source) or projections systems. 8.1 Power management The TDA8754 has two analog inputs (RGB input 1 and RGB input 2) selectable via the I2C-bus. The sync management can be achieved in several ways: * Choice between two analog inputs HSYNC and two analog inputs VSYNC * Choice between two analog inputs CHSYNC * Choice between two analog inputs SOG. 8.2.2 ACTIVITY DETECTION It is possible to put the TDA8754 in standby mode by setting bit STBY = 1 or to put the whole device in powerdown mode by setting pin PWD to HIGH level. 8.1.1 STANDBY MODE In standby mode, the status of the blocks is as follows: * Activity detection, I2C-bus slave, sync separator and SOG are still active * Pixel counter, ADCs, demultiplexers, AGC and clamp cells are inactive * Output buffers to the RGB block (RGB 0 to 7, CKDATA, DEO, HSYNCO and VSYNCO) are in high-impedance state * Output HPDO is still active * Output buffers (ROR, BOR, GOR, CKREFO, CSYNCO, CLPO and FIELDO) are in a LOW-level state. 8.1.2 POWER-DOWN MODE When a signal is connected or disconnected on pins HSYNC1(2), CHSYNC1(2), VSYNC1(2) and SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is set to HIGH to advise the user of a change. Bit HPDO is set to logic 0 and pin HPDO is set to LOW when register ACTIVITY2 has been read. When the synchronization pulse on pin SOG is 3-level, the system will automatically be able to detect that a 3-level sync is present and will force bit 3LEVEL to logic 1. It is possible to disable this function with bit FTRILEVEL. When an interlaced signal is detected, bit ACFIELD is set to logic 1. When the signal detected is progressive, this bit is set to logic 0. Any change in this bit results into setting bit HPDO = 1 and pin HPDO = HIGH. A field detection unit is available on pin FIELDO which output is given by the sync separator. The field identity is given by pin FIELDO. This pin gives the field of interlaced signal input. An automatic polarity detection is also available on pins HSYNC1(2), VSYNC1(2) and CHSYNC1(2). The output on pin HPDO is not affected by the change of polarity of these inputs. 8.2.3 ADC In power-down mode the status of the blocks is as follows: * All digital inputs and outputs are in high-impedance state * All blocks are inactive (I2C-bus, activity detection, ADCs, etc.) * Analog output is left uncontrolled * I2C-bus is left in high-impedance state. 8.2 Analog video input The RGB/YUV video inputs are externally AC coupled and are internally DC polarized. The synchronization signals are also used by the device as input for the internal PLL and the automatic clamp. The three ADCs are designed to convert R, G and B (or Y, U and V) signals at a maximum frequency of 270 Msps. The ADC input range is 1 V (p-p) full-scale and the pipeline delay is 2 ADC clock cycles from the input sampling to the data output. The reference ladders regulators are integrated. 2003 Sep 30 16 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 8.2.4 CLAMP TDA8754 properly in order to create the correct HSYNCO and DEO output signals (see Figs.5 and 6), which is depending on video standard. Output signal DEO should be used to determine the first active pixel. The demultiplexed mode should be used (bit DMX = 1) and the output flow is alternated between port A and port B in case the sampling frequency is over 140 Msps (clock frequency). It is necessary, in order to warrant that the outputs HSYNCO and DEO are always changing on CKDATA output rising edge (see Fig.7), that the values HSYNCL, HBACKL and HDISPL (see Fig.5) are even value. If an odd value is entered the outputs HSYNCO and DEO can change state during falling edge, which is not compliant with the th(o) and td(o) specified output timing. Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic 0 to a logic 1 a left move is obtained, also the timing relationship between HSYNCO, DEO and CKDATA stays unchanged. An even number of pixel moves is done by changing the value of HBACKL and HSYNCL. The correct combination of bits HBACKL, HSYNCL and SCHCKREFO places the first active pixel at the beginning of the screen with always the correct phase relationship between outputs DEO, HSYNCO and CKDATA. Bit HSOSEL should be set to a logic 0 only after the PLL is stable, so only after the video standard has been found and correct PLL parameters have been set in the TDA8754. Bit HSOSEL should be set to a logic 1 to have a stable HSYNCO signal during the video recognition. The video standard can be recognized by using the signals FIELDO, VSYNCO and HSYNCO. The phase relation between CKDATA and HSYNCO (or DEO) is undefined if bit HSOSEL = 1. 8.4 PLL Three independent parallel clamping circuits are used to clamp the video input signals on programmable black levels. The clamp levels may be set from -24 to +136 LSBs in steps of 1 LSB. They are controlled by three 9-bit I2C-bus registers (OFFSETR, OFFSETG and OFFSETB). The clamp pulse can be generated internally (based on the PLL clock reference) or can be externally applied on pin CLP. By setting correctly the I2C-bus bits, it is possible to inhibit the clamp request with the Vsync signal. This inhibition will be effected by forcing logic 0 on the clamp request output. It should be noted that the clamp period can start on the falling edge of the clamp request and that the high level of the clamp request sets the ADC outputs in the blanking mode. This means that by forcing the clamp signal request to logic 0 by using Vsync, a falling edge may happen on the clamp request if this signal was at logic 1 before enforcing the inhibition. To avoid this, the user has to guarantee that the Vsync signal used for the clamp inhibition will not be set during a high level of the clamp request signal. Remark: If signal Vsync is coming from the external pin VSYNC, this signal may be used to coast the PLL. In order to properly do the coast, the edge of signal Vsync (COAST) must not appear at the same time as the edge of signal Hsync. This condition is similar to the pin CLP inhibition condition. 8.2.5 AGC Three independent variable gain amplifiers are used to provide, for each channel, a full-scale input signal to the 8-bit ADC. The gain adjustment range is designed in such a way that for an input range varying from 0.5 to 1 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p). 8.3 HSOSEL, DEO and SCHCKREFO Bit HSOSEL allows to have a full correlation phase behaviour between outputs CKDATA and HSYNCO when bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and bits PA4 to PA0 of register PHASE are changed to chose the best sampling time, the phase relationship between outputs CKDATA and HSYNCO will stay unchanged. After the video standard is determined, bit HSOSEL must be set to a logic 0 for normal operation mode. To use the Hsync from the counter the registers HSYNCL, HBACKL, HDISPLMSB and HDISPLLSB should be set 2003 Sep 30 17 The ADCs are clocked by either the internal PLL locked to the reference clock (Hsync from input or Hsync from sync separator) or to an external clock connected to pin CKEXT. This selection is performed via the I2C-bus by setting bit CKEXT. To use the external clock, bit CKEXT must be reset to logic 1. The PLL phase frequency detector can be disconnected during the frame flyback (vertical blanking) or the unavailability of the Ckref signal by using the coast function. The coast signal can be derived from the VSYNC1(2) input, from the Vsync extracted by the sync separator or from the coast input. The coast function can be disabled with bit COE. Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps The coast signal may be active either HIGH or LOW by setting bit COS. It is possible to control the phase of the ADC clock via the I2C-bus with the included digital phase-shift controller. The phase register (5 bits) enables to shift the phase by steps of 11.25 deg. The PLL also provides a CKDATA clock. This clock is synchronized with the data outputs whatever the output mode is. It is possible to delay the CKDATA clock with a constant delay (t = 2 ns compared to the outputs) by setting bit CKDD = 1. Moreover, it is possible to invert this output by setting bit CKDATINV = 1. When the PLL reference signal comes from the separator, the PLL rising edge must be preferably used in order to not use the PLL coast mode. It should be noted that the TDA8754 HSYNCO output of the sync separator is always a mostly low signal, whatever is the polarity of the composite sync input. The VSYNCO output signal of the sync separator is also mostly low signal. It is at a high state during the vertical blanking. 8.5 Sync-on-green When the SOG input is selected (bit SOGSEL = 1), the SOG charge pump current bits SOGI[1:0] should be programmed in function of the input signal; see Table 1. A hum remover is implemented in the SOG. It removes completely the hum perturbation on the first or second edge of the horizontal sync pulse for digital video input like VESA, and on the second edge only for analog video input signal like TV or HDTV. The maximum hum perturbation is 250 mV (p-p) at 60 Hz to have a correct SOG functionality. Table 1 Charge pump current programming; note 1 MAXIMUM VALUE Tvideo / Tline 83.5 % 86.0 % 90.5 % test mode MAXIMUM VALUE Tsync / Tline 14.8 % 12.6 % 8.6 % STANDARD TV standards and non-VESA standards all TV, HDTV and VESA standards HDTV standards or non-VESA standards BITS SOGI[1:0] 00 01 10 11 Note 1. Definitions: Tvideo = total time in 2 frames when video signal is strictly superior to black level. Tline = total time of 2 frames. Tsync = total time in 2 frames when the video signal is strictly inferior to black level. 8.6 Programmable coast 8.7 Data enable When the values of PRECOAST[2:0] = 0 and POSTCOAST[4:0] = 0, the coast pulse equals the Vsync input. When an interlaced signal is used, the regenerated coast pulse width may vary from one frame to another of one Hsync pulse. In that case, the programmed value of PRECOAST[2:0] needs to be increased by one compared to the expected minimum number of Hsync coast pulses before the vertical sync signal. This signal qualifies the active data period on the horizontal line. Pin DEO = HIGH during the active display time and LOW during the blank time. The start of this signal can be adjusted with bits HSYNCL[9:0] and HBACKL[9:0]. The length of this signal can be adjusted with bits HDISPL[11:0]. 2003 Sep 30 18 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 8.8 Sync separator TDA8754 This function is able to get rid of the additional synchronization pulses in vertical blanking like egalisation or serration pulses. 8.9 3-level The sync separator is compatible with TV, HDTV and VESA standards. If the green video signal has composite sync on it (sync-on-green), the SOG function allows to separate the Chsync and the active video part. The Chsync signal coming from this SOG function is accessible through pin CSYNCO. It is possible to extract the Hsync and the Vsync signals by using the sync separator from this (C)Hsync signal coming from SOG or coming from the (C)Hsync input. 9 9.1 9.1.1 I2C-BUS REGISTER DESCRIPTION I2C-bus formats WRITE 1 REGISTER When the synchronization pulse of the input of the SOG is 3-level, the system will be able to detect that a 3-level sync is present and will advise the customer if a change is observed by setting bit HPDO = 1 and pin HPDO = HIGH. It is possible to disable this function with bit FTRILEVEL. When this automatic function is disabled, the manual mode will only influence the separator circuitry. Each register is programmed independently by giving its subaddress and its data content. Table 2 I2C-bus sequence for writing 1 register DESCRIPTION master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and subregister address to write to slave generates an acknowledge master transmits data 1 slave generates an acknowledge master generates a stop condition Byte format for writing 1 register 7 A6 1 Byte 2 - X Byte 3 D7 D6 D5 D4 6 A5 0 programming mode - X MODE 0 SA4 - data 1 D3 D2 D1 D0 SA3 - 5 A4 0 4 device address A3 1 A2 1 A1 0 register subaddress SA2 - SA1 - SA0 - A0 X 3 2 1 0 R/W - 0 SDA LINE S Byte 1 A Byte 2 A Byte 3 A P Table 3 BIT Byte 1 2003 Sep 30 19 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 4 BIT Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte 3 7 to 0 9.1.2 D[7:0] Data 1. This value is written in the selected register. - MODE SA[4:0] not used A[6:0] R/W Write format bit description SYMBOL DESCRIPTION TDA8754 Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level on pin A0. Write command bit. If R/W = 0, then write action. Mode selection bit. If MODE = 0, then each register can be written independently. Register subaddress. Subaddress of the selected register (from 0 0000 to 1 1111). WRITE ALL REGISTERS All registers are programmed one after the other, by giving this initial condition (XX11 1111) as the subaddress state; thus, the registers are charged following the predefined sequence of 32 bytes (from subaddress 0 0000 to 1 1111). Table 5 I2C-bus sequence for writing all registers DESCRIPTION master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and subregister address to start writing to slave generates an acknowledge master transmits data 1 slave generates an acknowledge : master transmits data 32 slave generates an acknowledge master generates a stop condition Byte format for writing all registers 7 A6 1 Byte 2 - X Byte (2 + n) D7 D6 D5 D4 6 A5 0 programming mode - X MODE 1 SA4 1 data n D3 D2 D1 D0 SA3 1 5 A4 0 4 device address A3 1 A2 1 A1 0 register subaddress SA2 1 SA1 1 SA0 1 A0 X 3 2 1 0 R/W - 0 SDA LINE S Byte 1 A Byte 2 A Byte 3 A : Byte 34 A P Table 6 BIT Byte 1 2003 Sep 30 20 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 7 BIT Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte (2 + n) 7 to 0 9.1.3 Table 8 D[7:0] READ REGISTER I2C-bus sequence for reading one register DESCRIPTION master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and subregister address to read from slave generates an acknowledge master transmits read register subaddress slave generates an acknowledge master transmits device address (7 bits) plus read command bit (R/W = 1) slave generates an acknowledge slave transmits data to master master generates an not-acknowledge after reading the data byte master generates a stop condition Data n. This value is written in register 00h + n. - MODE SA[4:0] not used A[6:0] R/W Write format bit description SYMBOL DESCRIPTION TDA8754 Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level on pin A0. Write command bit. If R/W = 0, then write action. Mode selection bit. If MODE = 1, then all registers can be written one after the other. Register subaddress. Initial condition is XX11 1111. SDA LINE S Byte 1 A Byte 2 A Byte 3 A Byte 4 A Byte 5 A P 2003 Sep 30 21 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 9 BIT Byte 1 A6 1 Byte 2 - X Byte 3 - 0 Byte 4 A6 1 Byte 5 D7 D6 D5 D4 A5 0 A4 0 - 0 - 0 A5 0 programming mode - X MODE 0 SA4 1 - 0 device address A3 1 data 1 D3 D2 D1 A2 1 A1 0 A0 X SA3 1 - 0 A4 0 Byte format for reading register 7 6 5 4 device address A3 1 A2 1 A1 0 register subaddress SA2 1 - 0 SA1 1 RA1 - A0 X 3 2 1 TDA8754 0 R/W - 0 SA0 1 RA0 - R/W - 1 D0 read subaddress Table 10 Read format bit description BIT Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte 3 7 to 0 Byte 4 7 to 1 0 Byte 5 7 to 0 D[7:0] Data 1. The value from read register is sent from the slave to the master. A[6:0] R/W Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level on pin A0. Read command bit. If R/W = 1, then read action. RA[1:0] Read address. This is the value of the read register to be selected. - MODE SA[4:0] not used Mode selection bit. If MODE = 0, then each register can be written independently. Register subaddress. Subaddress of the read register (1 1111). A[6:0] R/W Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level on pin A0. Write command bit. If R/W = 0, then write action. SYMBOL DESCRIPTION 2003 Sep 30 22 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 9.2 I2C-bus registers overview 2003 Sep 30 23 Philips Semiconductors Triple 8-bit video ADC up to 270 Msps Table 11 I2C-bus analog write registers MSB ADDR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h NAME 7 OFFSETR COARSER FINER OFFSETG COARSEG FINEG OFFSETB COARSEB FINEB SOG PLLCTRL PHASE DIVMSB DIVLSB HSYNCL HBACKL HDISPLMSB HDISPLLSB COAST HSYNCSEL VSYNCSEL CLAMP INVERTER OUTPUT OUTPUTEN1 OR7 OR8 - OG7 OG8 - OB7 OB8 - DO IP1 PA4 CKEXT DI7 CR6 - OG6 CG6 - OB6 CB6 - UP IP0 PA3 SCH CKREFO DI6 6 OR6 OR5 CR5 - OG5 CG5 - OB5 CB5 - Z2 PA2 EPSI1 DI5 5 OR4 CR4 - OG4 CG4 - OB4 CB4 - Z1 PA1 EPSI0 DI4 HSYNCL6 HBACKL8 HBACKL0 HDISPL4 POST COAST4 - CLPSEL1 CKREFO INV AGCSEL0 BOENRGB 4 OR3 CR3 - OG3 CG3 - OB3 CB3 - Z0 PA0 DI11 DI3 HSYNCL5 HBACKL7 HDISPL11 HDISPL3 POST COAST3 TESTCNT CLPH DEO INVRGB BLKEN AOENRGB 3 OR2 CR2 FR2 OG2 CG2 FG2 OB2 CB2 FB2 SOGSEL DR2 VCO2 DI10 DI2 HSYNCL4 HBACKL6 HDISPL10 HDISPL2 POST COAST2 BYSEPA VSS CLPENL HSO INVRGB DMXRGB OROEN 2 OR1 CR1 FR1 OG1 CG1 FG1 OB1 CB1 FB1 SOGI1 DR1 VCO1 DI9 DI1 HSYNCL3 HBACKL5 HDISPL9 HDISPL1 POST COAST1 HSSEL COSSEL2 ICLP VSO INVRGB ODDARGB TOUTERGB 1 OR0 CR0 FR0 OG0 CG0 FG0 OB0 CB0 FB0 SOGI0 DR0 VCO0 DI8 DI0 HSYNCL2 HBACKL4 HDISPL8 HDISPL0 POST COAST0 HSS COSSEL1 CLPT FIELDO INV SHIFTRGB TOUTSRGB 0 BIT LSB DEFAULT VALUE 0000 0000 0100 0110 XXXX X000 0000 0000 0100 0110 XXXX X000 0000 0000 0100 0110 XXXX X000 0000 0001 0101 1100 0000 0101 0000 0110 1001 1000 0010 0100 0000 1111 1000 0101 0000 0000 0000 0000 XXX X0100 XXX0 0000 X010 0000 X000 0000 0000 0000 XXX1 1100 FTRILEVEL STRILEVEL CKREFS HSYNCL9 HSYNCL8 HSYNCL7 HSYNCL1 HSYNCL0 HBACKL9 HBACKL3 HBACKL2 HBACKL1 HDISPL7 PRE COAST2 - - - - RGBSEL - HDISPL6 PRE COAST1 - - HSOSEL COS TEN - HDISPL5 PRE COAST0 - - CLPSEL2 CLPS AGCSEL1 - TSTCOAST COE Preliminary specification TDA8754 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Sep 30 24 Philips Semiconductors MSB ADDR 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh NAME 7 OUTPUTEN2 CLKOUTPUT INTOSC reserved reserved PWRMGT READADDR - - - - - - - - SHCKDMX - SHCKADC STBY - ADDR1 DVIRGB ADDR0 XXXX 0000 XXXX XX00 CKROEN - - 6 CSOEN - - 5 DEOEN RGB - - 4 HSOEN RGB CKSEL RGB - 3 HPDOEN DLYCLK RGB - 2 VSOEN RGB CKDAT INV - 1 CLPOEN OUT OSCILL SWITCH OSC 0 FIELDOEN CKOEN RGB INTOSC OFF BIT LSB DEFAULT VALUE 1111 1111 XXX0 0001 XXXX XX00 Triple 8-bit video ADC up to 270 Msps Table 12 I2C-bus analog read registers; note 1 MSB ADDR 1 2 3 4 Note 1. The read register address is specified with bits ADDR1 and ADDR0 of register READADDR. NAME 7 VERSION SIGN ACTIVITY1 ACTIVITY2 - - ACVS2 - - - ACVS1 ASD 6 - POLVS2 ACSOG2 3LEVEL 5 - POLVS1 ACSOG1 ACFIELD 4 VER3 POLCHS2 ACCHS2 HPDO 3 2 VER2 POLCHS1 ACCHS1 ACVSSEP 1 VER1 POLHS2 ACHS2 ACRXC1 0 VER0 POLHS1 ACHS1 ACRXC0 BIT LSB DEFAULT VALUE XXXX 0000 XX00 0000 0000 0000 X000 0000 Preliminary specification TDA8754 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.3 Offset registers (R, G and B) TDA8754 The offset registers contain a 9-bit value which controls the clamp level for the RGB channels. The 8 LSBs are in the offset registers and the 1 MSB is in the coarse gain control register. The relationship between the programming code and the level of the clamp code is given in Table 15. The default value is: clamp code = 0 and ADC output = 0. Table 13 Offset registers (00h, 03h, 06h) bit allocation REGISTER OFFSETR (00h) OFFSETG (03h) OFFSETB (06h) Default 7 OR7 OG7 OB7 0 6 OR6 OG6 OB6 0 5 OR5 OG5 OB5 0 4 OR4 OG4 OB4 0 3 OR3 OG3 OB3 0 2 OR2 OG2 OB2 0 1 OR1 OG1 OB1 0 0 OR0 OG0 OB0 0 Table 14 Offset registers (00h, 03h, 06h) bit description BIT SYMBOL DESCRIPTION OFFSETR (address: 00h) 7 to 0 OR[7:0] offset R channel; LSB in this register and MSB bit OR8 in register COARSER OFFSETG (address: 03h) 7 to 0 OG[7:0] offset G channel; LSB in this register and MSB bit OG8 in register COARSEG OFFSETB (address: 06h) 7 to 0 OB[7:0] offset B channel; LSB in this register and MSB bit OB8 in register COARSEB Table 15 Coding for clamp level and ADC output OR8 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0 HEX VALUE 1 E9 1 EA : 1 FF 0 00 0 01 : 0 3F 0 40 : 0 78 0 79 : 0 80 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0 OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 -24 -23 : -1 0 +1 : 63 64 : 120 121 : 128 -24/-23 -23/-22 : -1/0 0/1 1/2 : 63/64 64/65 : 120/121 121/122 : 128/129 CLAMP CODE (DECIMAL) ADC OUTPUT (CODE TRANSITION) 2003 Sep 30 25 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 OR8 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0 HEX VALUE : 0 86 0 87 9.4 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0 OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0 : 134 135 : 134/135 135/136 CLAMP CODE (DECIMAL) ADC OUTPUT (CODE TRANSITION) Coarse registers (R, G and B) The coarse gain of the AGC is controlled with 7 bits. The code gain can vary from 32 to 95; see Table 18. Table 16 Coarse gain registers (01h, 04h, 07h) bit allocation REGISTER COARSER (01h) COARSEG (04h) COARSEB (07h) Default 7 OR8 OG8 OB8 0 6 CR6 CG6 CB6 1 5 CR5 CG5 CB5 0 4 CR4 CG4 CB4 0 3 CR3 CG3 CB3 0 2 CR2 CG2 CB2 1 1 CR1 CG1 CB1 1 0 CR0 CG0 CB0 0 Table 17 Coarse gain registers (01h, 04h, 07h) bit description BIT SYMBOL DESCRIPTION COARSER (address: 01h) 7 6 to 0 OR8 CR[6:0] offset R channel; MSB bit of offset value coarse gain of the AGC for R channel COARSEG (address: 04h) 7 6 to 0 OG8 CG[6:0] offset G channel; MSB bit of offset value coarse gain of the AGC for G channel COARSEB (address: 07h) 7 6 to 0 OB8 CB[6:0] offset B channel; MSB bit of offset value coarse gain of the AGC for B channel Table 18 Coarse register CR6 DECIMAL VALUE 32 33 : 63 64 65 : 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 CR5 CR4 CR3 CR2 CR1 CR0 Vi TO BE FULL-SCALE GAIN ADC CG6 CG5 CG4 CG3 CG2 CG1 CG0 CB6 0 0 CB5 1 1 CB4 0 0 CB3 0 0 CB2 0 0 CB1 0 0 CB0 0 1 1.000 0.992 : 0.753 0.746 0.738 : 1.000 1.008 : 1.328 1.340 1.355 : 2003 Sep 30 26 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 CR6 DECIMAL VALUE 69 70 : 95 9.5 1 CR5 CR4 CR3 CR2 CR1 CR0 Vi TO BE FULL-SCALE GAIN ADC CG6 CG5 CG4 CG3 CG2 CG1 CG0 CB6 1 1 CB5 0 0 0 CB4 0 0 1 CB3 0 0 1 CB2 1 1 1 CB1 0 1 1 CB0 1 0 1 0.706 0.698 : 0.500 1.416 1.432 : 2.000 Fine registers (R, G and B) Fine gain control is done with 3 bits allowing 8 intermediate values between two values of consecutive coarse gain. Table 19 Fine gain registers (02h, 05h, 08h) bit allocation REGISTER FINER (02h) FINEG (05h) FINEB (08h) Default 7 - - - X 6 - - - X 5 - - - X 4 - - - X 3 - - - X 2 FR2 FG2 FB2 0 1 FR1 FG1 FB1 0 0 FR0 FG0 FB0 0 Table 20 Fine gain registers (02h, 05h, 08h) bit description BIT SYMBOL - FR[2:0] - FG[2:0] - FB[2:0] DESCRIPTION FINER (address: 02h) 7 to 3 2 to 0 not used fine gain of the AGC for R channel FINEG (address: 05h) 7 to 3 2 to 0 not used fine gain of the AGC for G channel FINEB (address: 08h) 7 to 3 2 to 0 not used fine gain of the AGC for B channel Table 21 Fine gain control bits (example for coarse register value 32) FR2 DECIMAL VALUE FG2 FB2 0 1 2 3 4 0 0 0 0 0 FR1 FG1 FB1 0 0 1 1 0 FR0 FG0 FB0 0 1 0 1 0 1.000 1.001 1.002 1.003 1.004 FINE STEPS OF GAIN ADC 2003 Sep 30 27 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 FR2 DECIMAL VALUE FG2 FB2 5 6 7 9.6 SOG register 0 0 1 FR1 FG1 FB1 0 1 1 FR0 FG0 FB0 1 0 1 1.005 1.006 1.007 FINE STEPS OF GAIN ADC Table 22 SOG (09h) bit allocation BIT Symbol Default 7 DO 0 6 UP 0 5 FTRILEVEL 0 4 STRILEVEL 0 3 CKREFS 0 2 SOGSEL 0 1 SOGI1 0 0 SOGI0 1 Table 23 SOG (09h) bit description BIT 7 SYMBOL DO 0 = default value 1 = forcing down 6 UP test bit for forcing charge pump current up 0 = default value 1 = forcing up 5 FTRILEVEL defines the 3-level function mode 0 = automatic 3-level 1 = level selection with bit STRILEVEL 4 STRILEVEL forces the state of 3-level function 0 = not 3-level mode 1 = 3-level mode 3 CKREFS enables the PLL Ckref signal to be selected 0 = same as input 1 = input inverted 2 SOGSEL enables the reference PLL between HSYNC input and SOG input to be selected 0 = HSYNC input 1 = SOG input 1 to 0 SOGI[1:0] defines the SOG charge pump current; values are given in % of sync pulse/line length 00 = 14,8 % maximum (TV standards) and non-VESA standards 01 = 12,6 % maximum (all standards) 10 = 8.6 % maximum (HDTV standards) and non-VESA standards 11 = 0 test mode DESCRIPTION test bit for forcing charge pump current down 2003 Sep 30 28 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.7 PLL control TDA8754 Table 24 PLLCTRL (0Ah) bit allocation BIT Symbol Default 7 IP1 0 6 IP0 1 5 Z2 0 4 Z1 1 3 Z0 1 2 DR2 1 1 DR1 0 0 DR0 0 Table 25 PLLCTRL (0Ah) bit description BIT 7 to 6 SYMBOL IP[1:0] 00 = 800 A 01 = 1200 A 10 = 1600 A 11 = 2000 A 5 to 3 Z[2:0] internal resistance value for the VCO filter to be selected 000 = not used 001 = 1.56 k 010 = 1.25 k 011 = 1.00 k 100 = 0.80 k 101 = 0.64 k 110 = 0.51 k 111 = 0.41 k 3 to 0 DR[2:0] PLL temperature phase drift to be compensated. The optimized value of this register is XX. These bits add a delay on the clock reference input of the PLL as a function of the temperature of the die. 000 = +1.75 step phase 001 = -0.3 step phase 010 = -4.3 step phase 011 = -6.2 step phase 100 = -2.2 step phase 9.8 Phase register DESCRIPTION charge pump current value to increase the bandwidth of the PLL Table 26 PHASE (0Bh) bit allocation BIT Symbol Default 7 PA4 0 6 PA3 0 5 PA2 0 4 PA1 0 3 PA0 0 2 VCO2 1 1 VCO1 0 0 VCO0 1 Table 27 PHASE (0Bh) bit description BIT 7 to 4 3 to 0 SYMBOL PA[4:0] VCO[2:0] VCO gain control. See Table 29. DESCRIPTION phase shift value for the clock pixel. See Table 28. 2003 Sep 30 29 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 28 Phase registers bits PA4 0 0 : 1 1 PA3 0 0 : 1 1 PA2 0 0 : 1 1 PA1 0 0 : 1 1 PA0 0 1 : 0 1 TDA8754 PHASE SHIFT (deg) 0 11.25 : 337.50 348.75 Table 29 VCO gain control VCO2 0 0 0 0 1 1 1 1 9.9 VCO1 0 0 1 1 0 0 1 1 VCO0 0 1 0 1 0 1 0 1 VCO GAIN (MHz/V) 13 30 60 60 105 105 135 no oscillation PIXEL CLOCK FREQUENCY (MHz) 12 to 22 22 to 45 45 to 62 62 to 85 85 to 120 120 to 176 176 to 270 - PLL divider registers Table 30 DIVMSB (0Ch) bit allocation BIT Symbol Default 7 CKEXT 0 6 SCH CKREFO 0 5 EPSI1 0 4 EPSI0 0 3 DI11 0 2 DI10 1 1 DI9 1 0 DI8 0 Table 31 DIVMSB (0Ch) bit description BIT 7 SYMBOL CKEXT external clock selection 0 = internal PLL 1 = external clock 6 SCH CKREFO shift of pixel counter reference (Ckref) with one clock pixel period 0 = not active 1 = active 5 to 4 EPSI[1:0] enables the resynchronization edge of CKREFO to be selected; they are test bits 00 = default value for proper operation : 11 = tbf 3 to 0 DI[11:8] PLL divider ratio. These are the 4 MSBs of the 12-bit value. See Table 34. DESCRIPTION 2003 Sep 30 30 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 32 DIVLSB (0Dh) bit allocation BIT Symbol Default 7 DI7 1 6 DI6 0 5 DI5 0 4 DI4 1 3 DI3 1 2 DI2 0 1 DI1 0 TDA8754 0 D0 0 Table 33 DIVLSB (0Dh) bit description BIT 7 to 0 SYMBOL DI[7:0] DESCRIPTION PLL divider ratio. These are the 8 LSBs of the 12-bit value. See Table 34. Table 34 PLL divider ratio DI11 DI10 0 : 1 9.10 0 : 1 DI9 0 : 1 DI8 0 : 1 DI7 0 : 1 DI6 1 : 1 DI5 1 : 1 DI4 0 : 1 DI3 0 : 1 DI2 1 : 1 DI1 0 : 1 DI0 0 : 1 PLL DIVIDER RATIO 100 : 4095 Horizontal sync registers Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be smaller than the PLL divider. Table 35 HSYNCL, HBACKL and HDISPL bits allocation BIT 7 6 5 4 3 2 1 0 Register address 0Eh Symbol Default HSYNCL9 0 HSYNCL8 0 HSYNCL7 1 HSYNCL6 0 HSYNCL5 0 HSYNCL4 1 HSYNCL3 0 HSYNCL2 0 Register address 0Fh Symbol Default HSYNCL1 0 HSYNCL0 0 HBACKL9 0 HBACKL8 0 HBACKL7 1 HBACKL6 1 HBACKL5 1 HBACKL4 1 Register address 10h Symbol Default HBACKL3 1 HBACKL2 0 HBACKL1 0 HBACKL0 0 HDISPL11 0 HDISPL10 1 HDISPL9 0 HDISPL8 1 Register address 11h Symbol Default HDISPL7 0 HDISPL6 0 HDISPL5 0 HDISPL4 0 HDISPL3 0 HDISPL2 0 HDISPL1 0 HDISPL0 0 Table 36 Sync registers (0Eh to 11h) bit description BIT - - - SYMBOL HSYNCL[9:0] HBACKL[9:0] HDISPL[11:0] DESCRIPTION length of the Hsync signal; in number of pixel clock cycles; minimum value is 16 interval between the Hsync active edge and the first active pixel; in number of pixels; minimum value is 16 number of active pixels for one line; length of the data enable signal; minimum value is 16 2003 Sep 30 31 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.11 Coast register TDA8754 Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals the VSYNC input. Table 37 COAST (12h) bit allocation BIT Symbol Default 7 PRE COAST2 0 6 PRE COAST1 0 5 PRE COAST0 0 4 POST COAST4 0 3 POST COAST3 0 2 POST COAST2 0 1 POST COAST1 0 0 POST COAST0 0 Table 38 COAST (12h) bit description BIT 7 to 5 4 to 0 SYMBOL DESCRIPTION PRE programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the COAST[2:0] vertical sync signal POST programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the COAST[4:0] vertical sync signal Horizontal sync selection register 9.12 Table 39 HSYNCSEL (13h) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 - X 3 TESTCNT 0 2 BYSEPA 1 1 HSSEL 0 0 HSS 0 Table 40 HSYNCSEL (13h) bit description BIT 7 to 4 3 - TESTCNT SYMBOL not used this bit is used to test the pixel counter 0 = normal mode 1 = test mode 2 BYSEPA enables the sync separator for the PLL reference to be bypassed 0 = Hsync from the separator 1 = bypass of the sync separator 1 HSSEL enables either the HSYNC or CHSYNC input signal to be selected 0 = HSYNC input 1 = CHSYNC input 0 HSS enables either the HSYNC or CHSYNC input signal to be inverted 0 = non-inverted 1 = inverted DESCRIPTION 2003 Sep 30 32 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.13 Vertical sync selection register TDA8754 Table 41 VSYNCSEL (14h) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 TSTCOAST 0 3 COE 0 2 VSS 0 1 COSSEL2 0 0 COSSEL1 0 Table 42 VSYNCSEL (14h) bit description BIT 7 to 5 4 - SYMBOL not used 0 = output of the separator function 1 = output of the coast function 3 COE enables coast mode 0 = coast mode 1 = no coast mode 2 VSS enables VSYNC input signal to be inverted 0 = non-inverted 1 = inverted 1 COSSEL2 selects signal for coast PLL mode 0 = signal selected with bit COSSEL1 1 = pin coast 0 COSSEL1 can be used for the coast PLL mode; see bit COSSEL2 0 = VSYNC input 1 = VSYNC from the sync separator 9.14 Clamp register DESCRIPTION TSTCOAST switches a multiplexer to select the output signal on pin VSYNCO Table 43 CLAMP (15h) bit allocation BIT Symbol Default 7 - X 6 HSOSEL 0 5 CLPSEL2 1 4 CLPSEL1 0 3 CLPH 0 2 CLPENL 0 1 ICLP 0 0 CLPT 0 Table 44 CLAMP (15h) bit description BIT 7 6 - HSOSEL SYMBOL not used defines the signal on the output HSYNCO; see Section 8.3 0 = Hsync from the Hcounter 1 = Ckref is reference of the PLL 5 CLPSEL2 can be used to select the clamp signal 0 = Hsync signal generated by the pixel counter 1 = signal selected with bit CLPSEL1 DESCRIPTION 2003 Sep 30 33 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 BIT 4 SYMBOL CLPSEL1 0 = PLL reference signal 1 = clamp input DESCRIPTION can be used to select the clamp signal; see bit CLPSEL2 3 CLPH inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 42) 0 = clamp inhibited during Vsynco 1 = clamp active during Vsynco 2 CLPENL defines if clamp input works on edge or on level 0 = on edge; for all frequencies (must be preferably chosen) 1 = on level; only for frequencies below 45 MHz to have proper clamp function 1 0 ICLP CLPT dedicated for test mode; should be forced to logic 0 defines if the test mode of the clamp is active 0 = not active 1 = active 9.15 Inverter register Table 45 INVERTER (16h) bit allocation BIT Symbol Default 7 - X 6 COS 0 5 CLPS 0 4 CKREFO INV 0 3 DEOINV RGB 0 2 HSOINV RGB 0 1 VSOINV RGB 0 0 FIELDO INV 0 Table 46 INVERTER (16h) bit description BIT 7 6 - COS SYMBOL not used enables the COAST input signal to be inverted 0 = non-inverted 1 = inverted 5 CLPS enables the CLAMP input signal to be inverted 0 = non-inverted 1 = inverted 4 CKREFOINV enables the output CKREFO to be inverted 0 = non-inverted 1 = inverted 3 DEOINVRGB enables the output DEO to be inverted 0 = non-inverted 1 = inverted 2 HSOINVRGB enables the output HSYNCO to be inverted 0 = non-inverted 1 = inverted DESCRIPTION 2003 Sep 30 34 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 BIT 1 SYMBOL VSOINVRGB 0 = non-inverted 1 = inverted DESCRIPTION enables the output VSYNCO to be inverted 0 FIELDOINV enables the output FIELDO to be inverted 0 = non-inverted 1 = inverted 9.16 Output register Table 47 OUTPUT (17h) bit allocation BIT Symbol Default 7 RGBSEL 0 6 TEN 0 5 AGCSEL1 0 4 AGCSEL0 0 3 BLKEN 0 2 DMXRGB 0 1 0 0 0 ODDARGB SHIFTRGB Table 48 OUTPUT (17h) bit description BIT 7 SYMBOL RGBSEL defines which RGB input will be used 0 = input 1 1 = input 2 6 TEN enables the track and hold operating mode to be selected 0 = mode enable; must be set to logic 0 for proper operation 1 = mode disable 5 to 4 AGCSEL[1:0] define the output on pin AGCO 00 = RAGC 01 = GAGC 10 = BAGC 11 = not used 3 BLKEN inhibits the blanking mode during clamp 0 = blanking active; during the blanking period, the RGB outputs of the ADC are fixed at the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater or equal to 0, or forced to 0 if these values are negative. 1 = blanking not active 2 DMXRGB determines whether all pixels go to port A or if pixels go alternately to port A and B. The maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode. 0 = port A 1 = port A and B 1 ODDARGB defines the parity of the pixels 0 = even pixel on port A 1 = odd pixel on port A 0 SHIFTRGB defines output on port A and B 0 = synchronous 1 = interleaved 2003 Sep 30 35 DESCRIPTION Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.17 Output enable register 1 TDA8754 Table 49 OUTPUTEN1 (18h) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 BOENRGB 1 3 AOENRGB 1 2 OROEN 1 1 0 0 0 TOUTERGB TOUTSRGB Table 50 OUTPUTEN1 (18h) bit description BIT 7 to 5 4 - BOENRGB SYMBOL not used enables output port B to be set to high-impedance 0 = active signal 1 = high-impedance 3 AOENRGB enables output port A to be set to high-impedance 0 = active signal 1 = high-impedance 2 OROEN enables outputs Out Of Range to be set to high-impedance 0 = active signal 1 = high-impedance 1 TOUTERGB defines if the test mode of the output buffer is active or not 0 = mode normal 1 = mode test 0 TOUTSRGB defines the state of the output in test mode 0 = forces output to LOW 1 = forces output to HIGH 9.18 Output enable register 2 DESCRIPTION Table 51 OUTPUTEN2 (19h) bit allocation BIT Symbol Default 7 CKROEN 1 6 CSOEN 1 5 1 4 1 3 1 2 VSOENRGB 1 1 CLPOEN 1 0 FIELDOEN 1 DEOENRGB HSOENRGB HPDOEN Table 52 OUTPUTEN2 (19h) bit description BIT 7 SYMBOL CKROEN 0 = active signal 1 = high-impedance 6 CSOEN enables the output CSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance DESCRIPTION enables the output CKREFO to be set to high-impedance 2003 Sep 30 36 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 BIT 5 SYMBOL DEOENRGB 0 = active signal 1 = high-impedance DESCRIPTION enables the output DEO to be set to high-impedance 4 HSOENRGB enables the output HSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance 3 HPDOEN enables the output HPDO to be set to high-impedance 0 = active signal 1 = high-impedance 2 VSOENRGB enables the output VSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance 1 CLPOEN enables the output CLPO to be set to high-impedance 0 = active signal 1 = high-impedance 0 FIELDOEN enables the output FIELDO to be set to high-impedance 0 = active signal 1 = high-impedance 9.19 Clock output register Table 53 CLKOUTPUT (1Ah) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 CKSELRGB 0 3 DLYCLKRGB 0 2 CKDATINV 0 1 OUTOSCILL 0 0 CKOENRGB 1 Table 54 CLKOUTPUT (1Ah) bit description BIT 7 to 5 4 - CKSELRGB SYMBOL not used enables the selection of the signal on the pin CKDATA 0 = clock of output buffers; signal Ckdata 1 = pixel clock of the converter; signal Ckadco 3 DLYCLKRGB enables a delay of 2 ns to be added to the clock Ckdata 0 = no delay 1 = 2 ns delay 2 CKDATINV enables the polarity of the output CKDATA to be inverted 0 = non-inverted 1 = inverted 1 OUTOSCILL enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the internal oscillator on the output 0 = Ckdata 1 = for test 2003 Sep 30 37 DESCRIPTION Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 BIT 0 SYMBOL CKOENRGB 0 = active signal 1 = high-impedance DESCRIPTION enables the output CKDATA to be set to high-impedance 9.20 Internal oscillator register Table 55 INTOSC (1Bh) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 - X 3 - X 2 - X 1 SWITCHOSC 0 0 INTOSCOFF 0 Table 56 INTOSC (1Bh) bit description BIT 7 to 2 1 - SWITCHOSC SYMBOL not used enables a multiplexer to be switched; signal insertion on the input of the separator and coast block, between the internal oscillator and pin CKEXT 0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = test mode 0 INTOSCOFF disables the internal oscillator for the separator function, the coast gate and activity detection 0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = disabled 9.21 Power management register DESCRIPTION Table 57 PWRMGT (1Eh) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 - X 3 0 2 0 1 STBY 0 0 DVIRGB 0 SHCKDMX SHCKADC Table 58 PWRMGT (1Eh) bit description BIT 7 to 4 3 2 1 - SHCKDMX SHCKADC STBY SYMBOL not used test bits; should be set to logic 0 for proper operation test bits; should be set to logic 1 for better performances enables the RGB block to be forced into the standby mode, except activity detection, I2C-bus registers. In the standby mode, all outputs are in high-impedance state, except pin HPDO which is still active. If the IC is in the power-down mode, this bit has no effect 0 = IC active 1 = standby mode 0 DVIRGB this bit must be set to logic 0 for proper operation DESCRIPTION 2003 Sep 30 38 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.22 Read register TDA8754 Table 59 READADDR (1Fh) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 - X 3 - X 2 - X 1 ADDR1 0 0 ADDR0 0 Table 60 READADDR (1Fh) bit description BIT 7 to 2 1 to 0 - ADDR[1:0] SYMBOL not used register address to be read 00 = read register 0 01 = read register 1 10 = read register 2 11 = read register 3 9.23 Version register DESCRIPTION Table 61 VERSION (01h) bit allocation BIT Symbol Default 7 - X 6 - X 5 - X 4 - X 3 VER3 0 2 VER2 0 1 VER1 0 0 VER0 0 Table 62 VERSION (01h) bit description BIT 7 to 4 3 to 0 - VER[3:0] SYMBOL not used version of the IC DESCRIPTION 2003 Sep 30 39 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.24 Sign detection register TDA8754 The sign bits are set at logic 0 when the input is a mostly low input signal. Table 63 SIGN bit allocation BIT Symbol Default 7 - X 6 - X 5 POLVS2 0 4 POLVS1 0 3 POLCHS2 0 2 POLCHS1 0 1 POLHS2 0 0 POLHS1 0 Table 64 SIGN bit description BIT 7 to 6 5 - POLVS2 SYMBOL not used sign of VSYNC2 input 0 = non inverted 1 = inverted 4 POLVS1 sign of VSYNC1 input 0 = non inverted 1 = inverted 3 POLCHS2 sign of CHSYNC2 input 0 = non inverted 1 = inverted 2 POLCHS1 sign of CHSYNC1 input 0 = non inverted 1 = inverted 1 POLHS2 sign of HSYNC2 input 0 = non inverted 1 = inverted 0 POLHS1 sign of HSYNC1 input 0 = non inverted 1 = inverted DESCRIPTION 2003 Sep 30 40 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.25 Activity detection register 1 TDA8754 Table 65 ACTIVITY1 bit allocation BIT Symbol Default 7 ACVS2 0 6 ACVS1 0 5 ACSOG2 0 4 ACSOG1 0 3 ACCHS2 0 2 ACCHS1 0 1 ACHS2 0 0 ACHS1 0 Table 66 ACTIVITY1 bit description BIT 7 ACVS2 SYMBOL activity of VSYNC2 input 0 = not active 1 = active 6 ACVS1 activity of VSYNC1 input 0 = not active 1 = active 5 ACSOG2 activity of SOGIN2 input 0 = not active 1 = active 4 ACSOG1 activity of SOGIN1 input 0 = not active 1 = active 3 ACCHS2 activity of CHSYNC2 input 0 = not active 1 = active 2 ACCHS1 activity of CHSYNC1 input 0 = not active 1 = active 1 ACHS2 activity of HSYNC2 input 0 = not active 1 = active 0 ACHS1 activity of HSYNC2 input 0 = not active 1 = active DESCRIPTION 2003 Sep 30 41 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 9.26 Activity detection register 2 TDA8754 It should be noted that activity, sign and polarity detection will be correctly set after a maximum delay of: 6 frame periods + 50 ms. Table 67 ACTIVITY2 bit allocation BIT Symbol Default 7 - X 6 ASD 0 5 3LEVEL 0 4 ACFIELD 0 3 HPDO 0 2 ACVSSEP 0 1 ACRXC1 0 0 ACRXC0 0 Table 68 ACTIVITY2 bit description BIT 7 6 - ASD SYMBOL not used indicates if parasite sync pulses have been detected 0 = not detected 1 = detected 5 3LEVEL state of the sync separator input 0 = Hsync 1 = 3-level Hsync 4 ACFIELD activity of the sync separator FIELDO output 0 = not active 1 = active 3 HPDO copy of the HPDO output state 0 = stable state on input 1 = new input 2 ACVSSEP activity of the sync separator (Vsync output) 0 = not active 1 = active 1 0 ACRXC1 ACRXC0 test bit test bit DESCRIPTION 2003 Sep 30 42 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC VCC Vi VTCK Io Tstg Tamb Tvj Vesd PARAMETER supply voltage supply voltage differences input voltage pin TCK input voltage output current storage temperature ambient temperature virtual junction temperature electrostatic discharge voltage HBM referred to VSSA referred to VSSA CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 - -55 0 - -2000 TDA8754 MAX. +5.5 +0.5 +5.5 +4.5 50 +150 70 150 +2000 V V V V UNIT mA C C C V 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient LQFP144 package LBGA208 package in free air 45 25 K/W K/W CONDITIONS VALUE UNIT 12 CHARACTERISTICS Typical values are measured at VCCA = VCCA(SOG) to GNDA(SOG) or VCCA(R) to GNDA(R) or VCCA(G) to GNDA(G) or VCCA(B) to GNDA(B) = 3.3 V; VCCD = VCCD(TTL) to GNDD(TTL) or VCCD(ADC) to GNDD(ADC) or VCCD(I2C) to GNDD(I2C) or VCCD(MCF) to GNDD(MCF) or VCCD(TTL) to GNDD(TTL) or VCCD(SLC) to GNDD(SLC) = 3.3 V; VCCO = VCCO(BB) to GNDO(BB) or VCCO(BA) to GNDO(BA) or VCCO(GB) to GNDO(GB) or VCCO(GA) to GNDO(GA) or VCCO(RB) to GNDO(RB) or VCCO(RA) to GNDO(RA) or VCCO(CLK) to GNDO(CLK) = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO VCC analog supply voltage digital supply voltage output stage supply voltage analog supply current digital supply current output stage supply current supply voltage difference VCCA to VCCD VCCO to VCCD VCCA to VCCO Ptot P total power dissipation power dissipation power-down mode standby mode 2003 Sep 30 43 -100 -165 -165 - - - - - - 1.0 10 120 +100 +165 +165 1.3 - - mV mV mV W mW mW 3.0 3.0 3.0 - - - 3.3 3.3 3.3 180 125 1 3.6 3.6 3.6 - - - V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL R, G and B amplifiers PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RGB INPUTS: PINS RIN1, GIN1, BIN1, RIN2, GIN2 AND BIN2 Vi(p-p) Ii Ci Ri AMPLIFIERS B Gc bandwidth coarse gain -3 dB; Tamb = 25 C maximum coarse gain; code = 95 G/T GE(rms) amplifier gain stability variation with temperature full-scale channel-to-channel matching (RMS value) - - 410 0 6 2 - - - - - 2.5 MHz dB dB % % minimum coarse gain; code = 32 - input voltage range (peak-to-peak value) input current input capacitance input resistance 0.5 -40 - 50 - - 3 - 1.0 +40 - - V A pF k minimum coarse gain; code = 32 - minimum coarse gain; code = 32 - R, G and B clamp Nclamp clamp level accuracy fCLK = 25MHz - - 2 LSB Phase-Locked Loop (PLL) PLL; see Table 69 JPLL(p-p) DR fPLL fref step step fs(max) INL DNL ENOB ct S/N SFDR THD long term PLL phase jitter (peak-to-peak value) divider ratio output clock frequency reference clock frequency phase drift phase shift step fclk = 270 MHz; DR = 2160 - 100 10 15 - - 270 fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz - - - - - 48 - 390 - - - - 11.25 - 0.6 0.25 7.6 - 48 55 -55 480 4095 270 150 2 - - 1.3 0.6 - -45 - - -48 MHz kHz step deg ps Analog-to-Digital Converters (ADCs); minimum coarse gain maximum sampling frequency integral non-linearity differential non-linearity effective number of bits crosstalk signal-to-noise ratio spurious free dynamic range total harmonic distortion MHz LSB LSB bits dB dB dB dB 2003 Sep 30 44 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 SYMBOL PARAMETER CONDITIONS MIN. - 1.9 - TYP. MAX. UNIT Data timing; 10 pF load; see Fig.4 td(o) th(o) tsu(o) output delay output hold time output setup time 4 - - 5.2 - 6.6 ns ns ns LV-TTL digital inputs and outputs INPUT PINS CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK AND CLP VIL VIH OUTPUT PINS LOW-level input voltage HIGH-level input voltage 0 2.0 - - 0.8 VCCD V V RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO, HSYNCO, VSYNCO, FIELDO, CLPO, CKREFO AND CSYNCO LOW-level output voltage HIGH-level output voltage IOH = 1 mA IOL = 1 mA - 2.4 - - 0.4 - V V VOL VOH Data clock output OUTPUT PIN CKDATA maximum buffer frequency - 140 - MHz fCKDATA(max) Data outputs OUTPUT PINS RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO AND CSYNCO maximum buffer frequency - 70 - MHz fdata(max) Hsync inputs INPUT PINS HSYNC1, HSYNC2, CHSYNC1 AND CHSYNC2 tW(Hsync)(min) tW(Hsync)(max) SOG inputs INPUT PINS SOGIN1 AND SOGIN2 Vsync(G) Vsync(G) sync-on-green pulse amplitude high/low differential amplitude of 3-level pulse 150 - - - - 20 mV % minimum pulse width maximum pulse width in % of total horizontal line 250 - - - - 20 ns % I2C-bus (fast mode; 5 V tolerant) PINS SCL AND SDA fSCL Cb clock frequency capacitive load - - - - 400 400 kHz pF 2003 Sep 30 45 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps Table 69 Examples of PLL settings and performance VCCA = VCCD = VCCO = 3.3 V; Tamb = 25 C; note 1. fref (kHz) 31.469 48.08 60.02 63.98 80.00 75.00 93.75 106.25 fclk (MHz) 25.175 50 78.75 108 135 162 202.5 229.5 KO (MHz/V) 30 60 60 105 105 105 135 135 CZ (nF) 220 220 220 220 220 220 220 220 CP (pF) 680 680 680 680 680 680 680 680 IP (A) 1200 1200 1600 1600 1600 2000 1600 2000 Z () 510 510 640 510 640 640 800 640 TDA8754 VIDEO STANDARD VGA 60 Hz VESA: 640 x 480 SVGA 72 Hz VESA: 800 x 600 XGA 75 Hz VESA: 1024 x 768 SXGA 60 Hz VESA: 1280 x 1024 SXGA 75 Hz VESA: 1280 x 1024 UXGA 60 Hz VESA: 1600 x 1200 UXGA 75 Hz VESA: 1600 x 1200 UXGA 85 Hz VESA: 1600 x 1200 Note DR 800 1040 1312 1688 1688 2160 2160 2160 LONG-TERM TIME JITTER RMS (ps) 500 370 220 185 145 135 95 85 p-p (ps) 3000 1980 1320 1110 870 810 570 510 1. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum. handbook, full pagewidth VOH CKDATA sample N + 1 sample N + 2 50 % VOL sample N RGB input th(o) RGB outputs A7 to A0, B7 to B0, DEO, HSYNCO, CKREFO VOH DATA N-2 DATA N-1 td(o) DATA N DATA N+1 50 % VOL MCE410 Fig.4 Data timing diagram. 2003 Sep 30 46 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Sep 30 R,G,B in 1 2 3 4 5 6 7 8 9 10 11 12 13 CS ckdivo ckphi ckrefin HSYNCL HBACKL 1 hb hb-1 1 hd 13 TIMING Philips Semiconductors possibility to add a clock period with bit SCHCKREFO HDISPL hd-1 hd-2 handbook, full pagewidth 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 Triple 8-bit video ADC up to 270 Msps 47 hcount hs hs-1 hs-2 hsyncin dein ckadco ADC out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MDB107 Preliminary specification TDA8754 HSYNCL, HBACKL and HDISPL must be long 16 (minimum value in number of pixel clock cycles). Fig.5 Timing diagram. Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 handbook, full pagewidth ckrefin HSYNCO CKREFO DEO CKDATA RGB outputs A7 to A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MDB201 HSCYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock pulses. Fig.6 Output format port A. handbook, full pagewidth ckrefin HSYNCO CKREFO DEO CKDATA bit SHIFTRGB = 0 RGB outputs A7 to A0 RGB outputs B7 to B0 RGB outputs A7 to A0 RGB outputs B7 to B0 28 2 4 6 8 10 12 14 16 18 27 1 3 5 7 9 11 13 15 17 bit SHIFTRGB = 1 28 2 4 6 8 10 12 14 16 18 27 1 3 5 7 9 11 13 15 17 19 MDB108 HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock pulses. Fig.7 Output formats ports A and B; even pixels port A and odd pixels port B. 2003 Sep 30 48 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 handbook, full pagewidth ckrefin HSYNCO CKREFO DEO CKDATA bit SHIFTRGB = 0 RGB outputs A7 to A0 RGB outputs B7 to B0 27 1 3 5 7 9 11 13 15 17 28 2 4 6 8 10 12 14 16 18 MDB200 HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock pulses. Fig.8 Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 0. handbook, full pagewidth ckrefin HSYNCO CKREFO DEO CKDATA bit SHIFTRGB = 1 RGB outputs A7 to A0 RGB outputs B7 to B0 27 1 3 5 7 9 11 13 15 17 28 2 4 6 8 10 12 14 16 18 MCE411 HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock pulses. Fig.9 Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 1. 2003 Sep 30 49 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 14 APPLICATION INFORMATION TDA8754 handbook, full pagewidth VCCD SCL SDA VCCD R21 4.7 k VCCD GNDD(SLC) CKEXT VCCD(SLC) R20 4.7 k VCCD GNDO(CLK) GNDD(I2C) A0 VCCD(I2C) VCCO GNDO(TTL) VSYNCO VCCO(TTL) VCCD GNDD(MCF) VCCD(MCF) VCCO VCCO CKDATA VCCO(CLK) GNDO(RA) VCCO(RA) 110 CKREFO STBYDIV CSYNCO HSYNCO VSYNC1 VSYNC2 FIELDO COAST ACRX1 ACRX2 HPDO DEO CPLO TDO SDA TCK CLP SCL 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 VCCD GNDD(TTL) VCCD(TTL) HSYNC2 CHSYNC2 VCCA(PLL) HSYNC1 CHSYNC1 GNDA(PLL) C1 220 nF CZ 109 RA7 DIS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ROR GNDO(RB) VCCO(RB) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 GNDO(GA) VCCO(GA) GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 GOR GNDO(GB) VCCO(GB) GB7 GB6 GB5 GB4 GB3 out green B out green A out red B out red A VCCA GNDA(CPO) CP C2 680 pF 1 F 1 F 330 pF PMO GNDA(SUB) C3 CAPSOGIN1 CAPSOGO C4 CAPSOGIN2 GNDA(SOG) SOGIN1 SOGIN2 VCCA RIN1 RIN2 C5 SOGIN1 VCCA(SOG) SOGIN2 VCCA(R) RIN1 GNDA(R1) C8 1 F 100 nF 100 nF 4.7 nF 1 F 1 F 100 nF 4.7 nF RIN2 GNDA(R2) C9 C10 C11 VCCA GIN1 DEC RBOT RCLPC VCCA(G) GIN1 GNDA(G1) GIN2 C13 GIN2 GNDA(G2) C14 C15 VCCA GBOT GCLPC VCCA(B) VCCO TDA8754HL 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 C6 330 pF 1 F VCCO C7 C12 VCCO BIN1 BIN2 BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 VCCO(BA) GB0 GB1 GNDA(B1) GNDA(B2) BBOT BCLPC AGCO GNDD(ADC) VCCD(ADC) GNDD(SUB) PWD TEST VCCO(BB) GNDO(BB) BOR GNDO(BA) GB2 out blue B out blue A MDB109 C16 1 F C17 1 F C18 100 nF C19 4.7 nF VCCD VCCO VCCO BIN1 BIN2 Fig.10 Application diagram. 2003 Sep 30 50 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 15 PACKAGE OUTLINES LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm TDA8754 SOT486-1 c y X A 108 109 73 72 ZE e E HE A A2 A1 (A 3) Lp L detail X wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7 0o o 22.15 22.15 21.85 21.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 2003 Sep 30 51 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps TDA8754 LBGA208: plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm SOT774-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e C b v M C A B w M C y1 C y T R P N M L K J H G F E D C B A 1/2 e e e2 ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.65 A1 0.45 0.35 A2 1.20 0.95 b 0.55 0.45 D 17.2 16.8 E 17.2 16.8 e 1 e1 15 e2 15 v 0.25 w 0.1 y 0.12 y1 0.35 OUTLINE VERSION SOT774-1 REFERENCES IEC --JEDEC MO-192 JEITA --- EUROPEAN PROJECTION ISSUE DATE 02-05-14 2003 Sep 30 52 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 16 SOLDERING 16.1 Introduction to soldering surface mount packages TDA8754 To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Sep 30 53 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 16.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP(8) Notes not suitable not suitable(4) TDA8754 SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable suitable not not recommended(5)(6) recommended(7) not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages. 2003 Sep 30 54 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 17 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION TDA8754 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Sep 30 55 Philips Semiconductors Preliminary specification Triple 8-bit video ADC up to 270 Msps 20 PURCHASE OF PHILIPS I2C COMPONENTS TDA8754 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Sep 30 56 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R78/04/pp57 Date of release: 2003 Sep 30 Document order number: 9397 750 12016 |
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